PhD Thesis Defense: Zhaoyang Yin

For Info on how to attend this videoconference, please email Zhaoyang Yin at zhaoyang.yin.TH@dartmouth.edu

"Robust and Low Power Readout Circuits for Quanta Image Sensors"

Abstract

Pixel shrinkage brings the benefits of lower costs for CMOS image sensors as the photon resolution increases. However, for sub-diffraction-limit (SDL) pixels, the signal-to-noise ratio (SNR) will be worse, and the dynamic range will be lower. This leads to worse image quality. Quanta image sensors (QIS) have been proposed to solve this problem. Readout circuitry is an important part in the QIS.

The previous readout circuit in a single-bit QIS is a 1-bit charge transfer amplifier (CTA)-based ADC. Its performance can be easily degraded due to the fluctuation of common-mode voltage of pixel output. A new readout architecture, a capacitive trans-impedance amplifier (CTIA) before a 1-bit CTA-based quantizer, for single-bit QIS is proposed. A single-bit QIS test chip based on the readout architecture is designed and fabricated. According to the measured D-log-H results, a good threshold uniformity in the range of 0.3 to 0.8 e- for all readout clusters is demonstrated at 500 frames per second (fps) equivalent timing with 68 mW power consumption. A coarse photon counting histogram (PCH) is obtained by sweeping quantizer threshold, showing a 0.35e- r.m.s. read noise (including jot and readout circuit noise).

However, the development of a single-bit QIS is not the final goal because a multi-bit QIS has several relative advantages. To explore the readout circuits in a multi-bit QIS, five well-known analog-to-digital converter (ADC) approaches (flash, pipeline, successive approximation register (SAR), cyclic and single-slope (SS)) are studied. Studies show that SAR ADC, and SS ADC are the ADCs with the better metric value. A 1024 × 896 test chip included those two kinds of ADCs is designed, fabricated and measured. Measurement results show that the power consumption of the SAR ADCs is better than that of the SS ADCs and decreases by a factor of 17 when the resolution is changed from 1 bit to 6 bits. By contrast, the power consumption of the SS ADCs does not benefit much from an increase in resolution. Thus, SAR ADCs may be more suitable for use in low-power multi-bit QIS in terms of power consumption.

Thesis Committee

• Eric. R. Fossum, PhD (Chair)
• Jason T. Stauth, PhD
• Kofi M. Odame, PhD
• Jiaju Ma, PhD

Contact

For more information, contact Theresa Fuller at theresa.d.fuller@dartmouth.edu.