Parasitic Capacitance Explained

Any chunk of CMOS circuitry can be modeled with resistance-capacitance networks. Each transistor is represented by a capacitance at the gate and a resistance across the channel. Wires (segments of metal or polysilicon) also have both a resistance and capacitance with respect to the substrate. Thus we can take the following simple circuit

and model it using RC networks, for the case in which the output switches from high to low.

Where V0 = Vdd, R0 and C0 represent the resistance and capacitance of the wire, R1 represents the resistance of the driving transistor channel, and C1 represents the capacitance of the gates being charged. If we lump these components together as R and C, we can calculate that the voltage across C1, which represents the input voltage of the second inverter, will go as

Vin2 = V0*exp(-t/RC)

The delay in the system is proportional to RC. For this reason, designers would like to minimize resistances and capacitances in CMOS circuits.

But how does one determine the resistance and capacitance of a wire?

Resistance is given by

R = (rho)L/tw

Where L, t, and w are the length, thickness and width of the wire. Since thickness is typically fixed by the fabrication technology, resistance is proportional to L/w, so we can refer to the resistance of wires in a given technology as x ohms/square. In terms of fabrication, the only factors which affect resistance are the resistivity of the wire material and its thickness.

To get an estimate of parasitic capacitance, we will use an oversimplified model. Consider a wire to be a parallel plate capacitor, with the substrate acting as the bottom plane. The equation for capacitance of a parallel plate arrangement is

C = (epsilon0)A/d

In this expression, d refers to the distance from the conducting substrate. This is the key factor which motivated the interest in silicon-on-insulator. Because, if we can increase the distance of the wires from the conducting plane of the substrate, or eliminate the conducting substrate altogether, capacitance can be significantly reduced. Since resistance is not affected, this indicates that we should be able to build faster circuits using SOI.

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