Proposed new course for Spring term, 2009

Engineering 199 — Advanced Digital System Design

Prerequisites: Engs 31, and one additional course in computer hardware (e.g., CoSc 37 or Engs 62) or signals and systems (e.g., Engs 110 (may be taken concurrently) or Engg 129).

Description: Field-programmable gate arrays (FPGAs) have become a major “fabric” for implementing digital system designs, rivaling application-specific integrated circuits (ASICs) and microprocessors/microcontrollers for many applications requiring high-speed special-purpose architectures, such as digital signal processing. Hardware description languages (HDLs) have become the dominant method for digital system design. This course will advance the student’s ability to do HDL-based design and use computer-aided tools to create effective implementations on FPGAs.

Engs 31 is the key prerequisite. The second prerequisite is intended to make sure the student has additional knowledge in either computer systems or signal processing. The ways in which this course extends the content of Engs 31 are listed in the following table:

Engs 31	Engg 199 (to become new 128)
FPGA architecture explored cursorily	All FPGA architectural features studied in depth
Elementary register-transfer level (RTL) design methods	Extensive treatment of RTL and IP cores.
Simple datapaths	Thorough treatment of fixed-point arithmetic, high-speed datapaths
Pre-synthesis behavioral simulation sufficient for design verification.	Design verification using post-implementation timing simulation.
Processor speed not critical	Maximize processor throughput through the use of pipelines, retiming, etc.
Synthesis and implementation (translating HDL to FPGA) are a “black box”.	Synthesis and implementation well understood and directed toward design optimization.

Learning objectives: Not quite learning objectives yet, but this is what the student will gain from the course:

1. A deeper understanding of HDL-based design, simulation, and implementation.

2. A thorough understanding of one particular FPGA (e.g., the Xilinx Spartan 3A-DSP), as a basis for comparing the architectures of other FPGAs.

3. Understand how the synthesis-implementation flow works, and how it may be controlled to achieve particular design goals (speed, space, power consumption, etc).

4. Methods for high-speed processor design, including fast arithmetic and pipelining, and application to a particular problem domain, e.g., audio compression or software-defined radio.

5. Using hierarchical design methods to manage a complex design project.

Major topics:

1. Digital system design methods: Fixed-point arithmetic, pipelined datapaths, exploiting FPGA architectural features. Structuring a design with reusable modules and IP cores.

2. Simulation, synthesis, and implementation: How to use EDA (electronic design automation) tools to effectively verify and implement a design on an FPGA fabric. Advanced use of testbenches, simulators, in-circuit debugging.

3. Applications in signal processing: Fast hardware for digital filters, Fourier transforms, multirate processing.

Text: P.P. Chu, RTL Hardware Design Using VHDL (Wiley/IEEE Press)

Xilinx product documentation

Reserve readings, including selections from U. Meyer-Baese, Digital Signal Processing with Field-Programmable Gate Arrays (Springer-Verlag)

Grading: The course will be organized around a progression of design exercises and a final project. No exams.

Design exercises (6) 60-65

Project 35-40

The design exercises are to be determined. Possibilities for the term project include a CPU core, software-defined radio, MP3 codec, JPEG codec, or something using an ethernet physical layer (PHY). It is anticipated that everyone in the class will do the same project.